Bi-directional amplifying bus-switch

ABSTRACT

A bus-switch which permits data-transmission with amplification therethrough in a predetermined one of two directions. Transmission in the established direction is maintained regardless of conditions at the output side of the switch until data applied to the switch from such direction ceases. This is achieved by a logic network which includes memory means for remembering the direction of transmission which has priority.

United States Patent [191 Foss et al.

[ Oct. 30, 1973 [541 BI-DIRECTIONAL AMPLIFYING BUS-SWITCH [75] Inventors: Richard C. Foss, Ottawa, Ontario;

Walter Spittle, Carp, Ontario, both of Canada [73] Assignee: Mlcrosystems International Limited,

Montreal, Quebec, Canada [22] Filed: Sept. 27, 1972 [21] Appl. No.: 292,620

3,393,382 7/1968 Myers 307/242 X 3,476,956 11/1969 Burgess et al 307/242 X 3,504,201 3/1970 Richardson 307/291 X 3,612,905 10/1971 Cook, Jr. 307/241 X 3,673,434 6/1972 McIntosh 307/289 X OTHER PUBLICATIONS Rosser, Using Two-State ICS With Ternary Signals, Electronic Engineering, September 1970, p. 84-87.

Primary Examiner-John W. Huckert Assistant Examiner-L. N. Anagnos AttorneyAlfred A. DeLuca [57] ABSTRACT A bus-switch which permits data-transmission with amplification therethrough in a predetermined one of two directions. Transmission in the established direction is maintained regardless of conditions at the output side of the switch until data applied to the switch from such direction ceases. This is achieved by a logic network which includes memory means for remembering the direction of transmission which has priority.

17 Claims, 10 Drawing Figures [56] References Cited UNITED STATES PATENTS 3,165,636 1/1965 Mellott 307/247 3,170,038 2/1965 Johnson et a1... 307/241 X 3,219,931 11/1965 Lennon et a1 307/242 X BLDIRECTIONAL AMPLIFYHNG BUS-SWKTCH The present invention relates to a bi-directional amplifying bus-switch.

There are many instances in the data-transmission art when it is necessary or desirable to transmit data in opposite directions and with amplification along a bus line. This requires two amplifying functions one for amplifying data transmitted in one direction and the other for amplifying data transmitted in the opposite direction. This use of two amplifiers in a single loop gives rise to a serious oscillation problem, and it is this problem which the present invention seeks to avoid.

According to the present invention there is provided a bi-directional bus switch circuit having first and second terminal means for series connection into a busline, first amplifying gate means having its input connected to said first terminal means, second logic gate means having first, second and third inputs, its second input connected to the output from said first amplifying gate means, enabling means and memory means for said circuit, the first and third inputs of said second logic gate connected to said enabling means and said memory means respectively, the output from said second logic gate means connected to said second terminal means, third amplifying gate means having its input connected to said second terminal means, fourth logic gate means having first, second and third inputs, its second input connected to the output from said third amplifying gate means, said first and third inputs of said fourth logic gate connected to said enabling means and said memory means respectively, the output from said fourth logic gate means connected to said first terminal means, whereby, when the direction of data transmission is established from one of said first and second terminal means to the other, said memory means applies and maintains an input to the respective logic gate associated with said direction of data transmission such that the output level thereof corresponds to the input level at said one terminal means when an enabling signal is applied to the first input of said respective logic gate, said memory means further applying and maintaining an input to the other said logic gate such that the output thereof is constant regardless of the data input level at said other of said first and second terminal means, said memory means so functioning until the flow of data transmission in said established direction ceases.

In a preferred embodiment of the invention, said memory means comprises seventh and eighth NAND gate means each having first and second inputs, said first input of said seventh NAND gate means connected to said first terminal means and said second input of said seventh NAND gate means connected to said second input of said fourth NAND gate means, said first input of said eighth NAND gate means connected to said second terminal means and said second input of said eighth NAND gate means connected to said second input of said second NAND gate means, the output of said seventh NAND gate means connected to a first inverting input of a fifth OR gate means, the output of said fifth OR gate means connected to a second inverting input of a sixth OR gate means, said sixth OR gate means having its output connected to a second inverting input of said fifth OR gate means and said sixth OR gate means having a second inverting input connected to the output of said eighth NAND gate means, the outputs of said fifth and sixth OR gate means being connected to the third inputs of said fourth and second NAND gate means respectively.

By De Morgans theorem, the invention also encompasses the obvious logical equivalents of the foregoing circuit elements and combinations thereof.

According to yet a further embodiment of the invention, a bi-directional bus-switch circuit comprises first and second terminal means for series connection into a bus-line, each of said first and second terminal means resistively coupled to means for connection to a power supply rail, said first terminal means connected through a fifth controllable switch means to means for connection to a reference ground potential rail and said second terminal means connected through a seventh controllable switch means to means for connection to said reference ground potential rail, fifth and sixth diode means series connected between said first terminal means and the control electrode of a third controllable switch means, second and third diode means series connected between said second terminal means and the control electrode of a fourth controllable switch means, fifth resistive means connected between means for connection to said potential supply rail and fourth diode means, the junction between said fifth resistive means and said fourth diode means being connected through said third controllable switch means to the control electrode of an eighth controllable switch means, said junction between said fifth resistive means and said fourth diode means beingfurther connected through first and sixth controllable switch means to meansfor connection to said reference ground potential rail, sixth resistive means connected between means for connection to said potential supply rail and firstdiode means, the junction between said sixth resistive means and said first diode means being connected through said fourth controllable switch means to the control electrode of said sixth controllable switch means, said junction between said sixth resistive means and said first diode means being further connected through second and said eighth controllable switch means to means for connection to said reference ground potential rail, the side of said fourth diode means remote from said fifth resistive means connected to the control electrode of said second controllable switch means and the side of said first diode means remote from said sixth resistive means connected to the control electrode of said first controllable switch means, the junction of said first and sixth controllable switch means connected to the control electrode of said fifth controllable switch means and the junction of said second and eighth controllable switch means connected to the control electrode of said seventh controllable switch means, third and fourth resistive means connecting the junctions between said fifth and sixth and said second and third diode means respectively to means for connection to said potential supply rail and means connected to the control electrodes of said third and fourth controllable switch means for connection to a pulse potential supply means for selectively enabling and disabling said third and fourth controllable switch means. i

in yet a further embodiment of the invention the aforesaid controllable switch means are bipolar transistors, the diode means are diodes and the resistive means are resistors.

The invention will now be described further by way of example only and with reference to the accompanying drawings, wherein:

FIG. 1 shows a bi-directional circuit with amplification according to the prior art;

FIG. 2 shows the prior art circuit of FIG. 1 with logic gates inserted therein according to the present invention; and

FIGS. 3, 4, 5(a, b and c), 6, 7 and 8 show bus-switch circuits according to various embodiments of the invention.

Referring now to the drawings, and particularly FIG. 1 thereof, there is shown a bus line having terminals A and B and two amplifiers l0 and 1 I connected in parallel and inserted in the line, amplifier 10 for amplifying data transmitted from B to A and amplifier 11 for amplifying data'transmitted from A to B. Immediately it will be seen that the loop formed by these amplifiers will quickly cause oscillation, effectively blocking accurate data transmission in either direction.

In the present invention, amplifier 11 is efiectively disabled while data is being transmitted from B to A and amplifier 10 is disabled while data is being trans mitted from A to B. This is accomplished by inserting a logic gate 12 or 13 in series with each respective amplifier, as shown in FIG. 2. One input to logic gate 12 is connected to terminal B and the other input to a terminal C. Similarly, one input to logic gate 13 is connected to terminal A and the input to a terminal D. Terminals C and D are connected to memory means for remembering which direction data transmission has been established and for ensuring that the logic gate controlling data flow in that direction remains enabled and the logic gate controlling data flow in the opposite direction is disabled until data flow in the originally established direction ceases.

In FIG. 2, gates 12 and 13 are shown as AND gates, but they may be any of the well known logic function gates depending upon the nature of the signals applied to terminal C and D from the memory means.

In the following description logic gates are extensively involved. Therefore, before proceeding further, a definition of such gates is given at this point.

A NAND gate is one wherein a LOW output is obtained only if all inputs are HIGH otherwise the output is HIGH.

An OR gate is one wherein a HIGH output is obtained only if one or more inputs are HIGH.

A realization of the circuit of FIG. 2 is shown in FIG. 3. The amplifier 10 and gate 12 of FIG. 2 are replaced in FIG. 3 by a NAND gate G and an amplifying inverter G Similarly, the amplifier l1 and gate 13 are replaced by a NAND gate 0 and an amplifying inverter 0,. An enabling input signal source for gates G and G, is connected to terminal T The third inputs of gates G and G are connected to a memory means M M2.

In FIG. 4, the memory means comprises a. flip-flop comprising two cross-coupled inverting input OR gates G and G the output node I of G being connected to an input to G, and the output node II of G being connected to an input to G The second input of inverting input OR gate 0,, is connected to the output of a NAND gate (3-,, one input of which is connected to terminal A and the other is connected to the output of G Similarly, the second input of inverting input OR gate 6,, is connected to the output of a NAND gate G one input of which is connected to terminal B and the other is connected to the output of G The circuit operates as follows. Initially, both terminals A and B are pulled to a potential HIGH rail through resistors R and R and terminals T and T Let terminal B now be pulled to LOW condition by application of data thereto. Now G inputs are HIGH (derived from the output of G and HIGH (derived from terminal A). The output of G is therefore LOW, which is applied to the inverting input of G The output of G and therefore node I is HIGH, and node II is consequently LOW. The inputs to G, are now HIGH (derived from node I), HIGH (derived from G and when'T is fedwith a HIGH enabling signal HIGH. Therefore, an amplified LOW signal is obtained at the output of G Checking G the input derived from node II is LOW and the output is therefore HIGH i.e., G is disabled.

Regardless of terminal A now going LOW, the input to G derived from terminal 8 is LOW until the condition of this terminal changes. Therefore the output from G, remains HIGH, ensuring two HIGH inputs to G and ensuring a LOW output therefrom at node II. Thus, the switch maintains its transmission of data from B to A, regardless of the state of terminal A, until terminal B returns to a HIGH level.

It will be appreciated that the logic circuit of FIG. 4 may equally well be represented in terms of its logic equivalents. For example, gate 6, could be an AND gate and the input of gate G made non-inverting. Taking this variation further, gate G could have both inputs non-inverting and the output inverting, whereupon the input to 6., connected to node I would be inverting. The second input to G, can also be inverting if the input to G connected thereto is inverting and G is noninverting. The third input to G can be inverting if the enable input from T is LOW instead of HIGH. Now we have three inverting inputs to G, and an inverting output. This is, of course, by De Morgans theorem, an OR gate. Exactly equivalent substitutions and modifications to the remaining gates in the circuit can be made having regard to the symmetry of the circuit. Also, according to De Morgans theorem, the logical inverse function with HIGH and LOW states interchanged may be constructed.

FIG. 5A shows each of gates G to G inclusive of FIG. 4 in circuit block form. Each gate comprises a controllable switch means 8,, having multiple inputs 1,, I I etc. The number of inputs provided is dependant upon the number of inputs required i.e., G and (3:; only have one operative input, G and G have three operative inputs and G to G inclusive have two operative inputs. All operative inputs must be HIGH before an output from S is obtained. The control electrode of S is connected through resistive means R to a potential supply rail PSR. The output of S is connected to the control electrode of a controllable switch means S the input of which is connected through resistive means R to potential supply rail PSR and the output of which is connected through resistive means R to reference ground potential. The output O/P from the gate is derived from the input of S The circuit operates as follows. When all inputs 1,, I 1:, are HIGH an output is derived from 8,, which enables S The output node 0/? derived from the potential supply rail PSR and which would normally be HIGH is now pulled down to LOW condition since S m is draining current to ground.

Therefore is LOW when all of 1,, 1 I etc. are HIGH.

The circuit of FIG. A may be conveniently realized in two TTL (transistor-transistor-logic) forms, the first of which is shown in FIG. 5B and is applicable to gates G G and G to G of FIG. 4 inclusive. Switch 5,, of FIG. SA is now realized by transistor Q15, which has multiple emitters connected to inputs I and I Obviously, as many emitters as are required may be provided. The second switch means of FIG. 5A is realized by the network comprising transistors Q Q and Q diode D and resistors R R R and R When all of I,, I etc are HIGH, an output is derived from Q which is applied to the base of Q enabling 0, The values of resistors R and R are such that when Q is conducting, sufficient charge is applied to the bases of Q and 0, to enable them. Now the output node is connected to the PSR rail through resistor R and diode D and to the ground rail through resistor R The ratio of the series combination of R and D to R is so chosen that in this condition, the output node will be nearer ground, i.e., LOW. Suppose now that any or all of l l etc. are LOW. Now the output from Q15 Will be LOW and Q will be disabled. In this situation charge will be applied to the base of Q and Q11 Will be enabled. Clearly, Q will be disabled. Now, the output node swings HIGH as current is drawn from PSR through R and D Turning now to FIG. 5C, an open-collector TTL gate which may be used for switches G and G, if FIG. 4 is shown. Transistors Q Q and Q1 are similar to those of FIG. 5B and are likewise designated. However, bearing in mind the function of each of gates G and G is to selectively pull the nodes of respective terminals A and B LOW (see FIG. 4), the circuit of FIG. 5C has an open-collector configuration for output transistor Q Thus, when all inputs 1,, I etc. of Q are HIGH, Q is enabled and with resistors R and R appropriately ratioed Q is also enabled. As a result the output node O/P is connected to ground and related terminal A (for G or B (for G is also connected to ground. If now any or all of I,, I etc. are LOW, Q is disabled and as a result, Q is also disabled, thereby allowing output node 0/? to rise.

Referring now to FIG. 6, a circuit in block form according to a further embodiment of the invention has terminals A and B for connection into a bus-line. Normally, each of terminals A and B is held HIGI-I, being pulled to the value of a potential supply rail PSR through a resistor R, or R respectively. Terminal A is also connected through a controllable switch means S to a reference ground potential rail. Series connected between the potential supply rail PSR and a reference ground potential rail are a resistive means R a controllable switch means S and a controllable switch means S respectively. The control electrode of controllable switch means S connected to the junction between S, and S The junction between R and S is connected through a diode means D to the control electrode of a controllable switch means S Series connected between the potential supply rail PSR and ground are respectively a resistive means R the controllable switch means S and a controllable switch means S The junction between R and S is connected through a diode means D to the control electrode of controllable switch means 5,. Terminal B is connected through a controllable switch means S to the reference ground potential rail and the control electrode of S is connected to the junction of S and S The junction of D, and R is connected through a controllable switch means 8., to the control electrode of S and the junction of R and D is connected through a controllable switch means 5;, to the junction of S The control electrode of S is connected through back-to-back diodes D and D to terminal B and the control electrode of S is connected through back-to-back diodes D and D to terminal A. The control electrodes of S and 5., are also connected to an enable/disable signal supply source, designated E,E. The junction between diodes D and D is connected through resistive means R to the PSR rail and the junction between diodes D and D e is connected to the PSR rail through resistive means R Referring to FIG. 7, a realization of the circuit of FIG. 6 is shown. Again, each of terminals A and B is normally held I-lIGI-l, being pulled up to the potential supply rail PSR through a resistor R or R respectively. Typically, the potential supply rail is at +5 volts. Terminal A is also connected through the collector-emitter path of a transistor Q to a reference ground potential rail. The base of Q is connected through the emittercollector path of a transistor 0, to a diode D and one end of a resistor R the other end of which is connected to the potential supply rail. The base of O is also connected through the collector-emitter path of a transistor O to the reference ground potential rail. The base of O is connected through the emitter-collector path of a transistor Q and a diode D to the base of transistor 0,. The base of transistor 0., is connected to terminal B through back-to-back diodes D and D the junction between said diodes being connected to the potential supply rail through a resistor R Terminal B is connected through the collectoremitter junction of a transistor O to a reference ground potential rail. The base of Q, is connected through the emitter-collector path of a transistor Q to diode D and one end of a resistor R the other end of which is connected to the potential supply rail. The base of Q, is also connected through the collectoremitter path of a transistor O to the reference ground potential rail. The base of transistor O is connected through the emitter-collector path of a transistor Q and diode D to the base of transistor Q The base of transistor O is connected through back-to-back diodes D and D to terminal A, the junction between D and D being connected to the potential supply rail through a resistor R The base electrode of each of transistors Q and Q, is connected to a disabling signal input E, E. This is derived from a suitable input buffer accepting standard input logic signals and delivering current outputs into Q and Q base electrodes when it is desired that no transmission of data in either direction shall occur. This current turns on Q and Q and, hence, Q and Q ensuring that Q1, Q5, Q2 and Q, are all disabled. This inhibits transmission of data in either direction.

Suppose now however, that the disabling current is not fed to Q and Q The circuit then operates as follows. Let both the inputs at A and B be I-IIGI-l. Suppose the input B now goes LOW. Current is now drawn through resistors R and R Assume that LOW level is reference ground potential and that one diode potential drop V is approximately equivalent to one baseemitter potential drop in any conducting transistor, i.e., V When B was HIGH, the potential at the anode of diode D was'3V (one diode drop across D and one V drop across each of Q and Q6)- When B goes LOW approaching zero the potential at the anode of D is now only V i.e., the drop across D Thus, the potential at the base of Q, is essentially at ground'and Q, is therefore disabled. Thus, no potential appears at the base of Q and O is disabled. Because Q, is disabled current in R can now flow into the path comprising diode D and the base-emitter junctions of Q, and Q Transistor 0,, now conducts, pulling terminal A down to reference ground potential. Since A is now at reference ground potential or LOW the potential at the base of Q goes to approximately ground, disabling Q and hence Q However, since there is still a current path through diode D and the base-emitter junction of Q, and Q; to ground, the junction of resistor R and the collector of are only one V drop through Q above ground potential. Thus, the potential appearing at the base of Q is essentially zero, since there is a diode drop across D Thus, no current path is established through 0 and Q remains disabled, maintaining point B in isolation from the reference ground potential rail. Therefore, transmission of data through the circuit from B to A is established regardless of the state of terminal A, until either a disabling signal is inputted or terminal B goes HIGH again.

Turning now to FIG. 8, there is shown a further embodiment of the invention wherein the novel bidirectional bus switch is in circuit form particularly suitable for integrated circuit fabrication techniques. The circuit is similar to that of FIG. 7 and like elements in FIGS. 7 and 8 are designated by like references.

The circuit of FIG. 8 contains the following elements which do not appear in FIG. 7. Schottky diodes SD and SD connected between the reference ground potential rail and terminals A and B respectively are antiringing devices which clamp the input line to one Schottky diode drop below reference ground potential. Transistors Q13 and Q are used in place of diodes D and D respectively, reducing the input current required. The only input current required is the base current drive on each of (I) and Q Transistor Q, and diode D in H6. 7 are replaced by transistors Q and O in H6. 8. Similarly, transistors Q and Q replace transistor Q and diode D in FIG; 7. The purpose of these substitutions is to provide Darlington pairs Q Q and Q 0 which are faster switching, easier to fabricate in integrated circuit form and have'better gain characteristics than the transistor diode combination. Each of resistors R R R and R are to em sure that the transistors with which they are associated i.e., Q Q Q and Q are more rapidly and completely disabled by pulling their base towards to reference ground potential. Finally, it will be noted that the majority of transistors used in the circuit of FIG. 8 are Schottky clamped transistors, which provide faster switching than conventional types.

Various alternatives and modifications to the embodiments disclosed herein will be readily apparent to those skilled in the art without departing from the spirit and scope of the invention as described by the disclosure and defined by the claims appended hereto.

What is claimed is:

ll. A bi-directional bus switch circuit having first and second terminal means for series connection into a busline, first amplifying gate means having input and output parts, its input part connected to said first terminal means, second logic gate means having an output part and first, second and third input parts, its second input part connected to said output part of said first amplifying gate means, enabling means and memory means for said circuit, said first and third input parts of said second logic gate means connected to said enabling means and said memory means respectively, said output part of said second logic gate means connected to said second terminal means, third amplifying gate means having input and output parts, its input part connected to said second terminal means, fourth logic gate means having an output part and first, second and third input parts, its second input connected to the output from said third amplifying gate means, said first and third inputs of said fourth logic gate connected to said enabling means and said memory means respectively, said output part of said fourth logic gate means connected to said first terminal means;

whereby, when the direction of data transmission is established from one of said first and second terminal means to the other, said memory means applies and maintains an input to the respective logic gate associated with said direction of data transmission such that the output level thereof corresponds to the input level at said one terminal means when an enabling signal is applied to the first input part of said respective logic gate, said memory means further applying and maintaining an input to the other said logic gate such that the output thereof is constant regardless of the data input level at said other of said first and second terminal means, said memory means so functioning until the flow of data transmission in said established direction ceases;

2. The invention as defined in claim 1 wherein the first and third amplifying gate means are inverting gates, and wherein the second and fourth logic gate means are NAND gates.

3. The circuit of claim 2 wherein said memory means comprises seventh and eighth logic gate means each having first and second input parts, said first input part of said seventh logic gate means connected to said first terminal means and said second input part of said seventh logic gate means connected to said second input part of said fourth NAND gate means, said first input part of said eighth logic gate means connected to said second terminal means and said second input part of said eighth logic gate means connected to said second input part of said second NAND gate means, said memory means also comprises a fifth and sixth logic gate means cross connected as a storage element or flipflop, the output part of said seventh logic gate means connected to a first input part of the fifth logic gate means, the output part of said fifth logic gate means connected to a second input part of the sixth logic gate means, said sixth logic gate means having its output part connected to a second input part of said fifth logic gate means and said sixth logic gate means having a first input part connected to the output part of said eighth logic gate means, the output parts of said fifth and sixth logic gate means being connected to the third input parts of said fourth and second NAND gate means respectively;

4. The circuit as defined in claim 3 wherein the seventh and eighth logic gate means are NAND gates and wherein the fifth and sixth logic gate means are OR gates with inverting input parts.

5. The circuit as defined in claim 3 wherein the seventh and eighth logic gate means are NAND gates and wherein the fifth and sixth logic gate means are AND gates with inverting input parts.

6. The circuit as defined in claim 3 wherein the seventh and eighth logic gate means are NAND gates and wherein the fifth and sixth logic gate means are NAND gates.

7. The circuit as defined in claim 3 wherein the seventh and eighth logic gate means are NAND gates and wherein the fifth and sixth logic gate means are NOR gates.

8. The invention as defined in claim 2 wherein said memory means comprises seventh and eighth logic gate means, each having first and second input parts, said first input part of said seventh logic gate means connected to said first terminal means and said second input part of said seventh logic gate means connected to said second input part of said fourth NAND gate means, said first input part of said eighth logic gate means connected to said second terminal means and said second input part of said eighth logic gate means connected to said second input part of said second NAND gate means, said memory means also comprises a fifth and a sixth logic gate means cross connected as a storage element or flip-flop, the output part of said seventh logic gate means connected to a first input part of the fifth logic gate means, the output part of said fifth logic gate means connected to a second input part of the sixth logic gate means, said sixth logic gate means having its output part connected to a second input part of said fifth logic gate means and said sxith logic gate means having a first input part connected to the output part of said eighth logic gate means, the output parts of said fifth and sixth logic gate means being connected to the third input parts of said second and fourth NAND gate means respectively.

9. The circuit as defined in claim 8 wherein the seventh and eighth logic gate means are AND gates and wherein the fifth and sixth logic gate means are NOR gates.

10. The circuit as defined in claim 8 wherein the seventh and eighth logic gate means are AND gates and wherein the fifth and sixth logic gate means are NAND gates.

11. The circuit as defined in claim 8 wherein the seventh and eighth logic gate means are AND gates and wherein the fifth and sixth logic gate means are OR gates with inverting input parts.

12. The circuit as defined in claim 8 wherein the seventh and eighth logic gate means are AND gates and wherein the fifth and sixth logic gate means are AND gates with inverting input parts.

13. The invention as defined in claim 1 wherein the first and third amplifying gate means are non-inverting gates, and wherein the second and fourth logic gate means are NOR gates.

14. A bi-directional bus switch circuit comprising first and second terminal means for series connection into a bus-line, each of said first and second terminal 10 means resistively coupled to means for connection to a power supply rail, said first terminal means connected through a fifth controllable switch means to means for connection to a reference ground potential rail and said second terminal means connected through a seventh controllable switch means to means for connection to said reference ground potential rail, fifth and sixth diode means series connected between said first terminal means and the control electrode of a third controllable switch means, second and third diode means series connected between said second terminal means and the control electrode of a fourth controllable switch means, fifth resistive means connected between means for connection to said potential supply rail and fourth diode means, the junction between said fifth resistive means and said fourth diode mean's'being connected through said third controllable switch means to the control electrode of an eighth controllable switch means, said junction between said fifth resistive means and said fourth diode means being further connected through first and sixth controllable switch means to means for connection to said reference ground potential rail, sixth resistive means connected between means for connection to said potential supply rail and first diode means, the junction between said sixth resistive means and said first diode means being connected through said fourth controllable switch means to the control electrode of said sixth controllable switch means, said junction between said sixth resistive means and said first diode means being further connected through second and said eighth controllable switch means to means for connection to said reference ground potential rail, the side of said fourth diode means remote from said fifth resistive means connected to the control electrode of said second controllable switch means and'the side of said first diode means remote from said sixth resistive means connected to the control electrode of said first controllable switch means, the junction of said first and sixth controllable switch means connected to the control electrode of said fifth controllable switch means and the junction of said second and eighth controllable switch means connected to the control electrode of said seventh controllable switch means, third and fourth resistive means connecting the junctions between said fifth and sixth and said second and third diode means respectively to means for connection to said potential supply rail and means connected to the control electrodes of said third and fourth controllable switch means for connection to a pulse potential supply means for selectively enabling and disabling said third and fourth controllable switch means.

15. The circuit of claim 14 wherein said controllable switch means are .bipolar transistors.

16. The circuit of claim 14 wherein said diode means are diodes.

17. The circuit of claim 14 wherein said resistive means are resistors. 

1. A bi-directional bus switch circuit having first and second terminal means for series connection into a bus-line, first amplifying gate means having input and output parts, its input part connected to said first terminal means, second logic gate means having an output part and first, second and third input parts, its second input part connected to said output part of said first amplifying gate means, enabling means and memory means for said circuit, said first and third input parts of said second logic gate means connected to said enabling means and said memory means respectively, said output part of said second logic gate means connected to said second terminal means, third amplifying gate means having input and output parts, its input part connected to said second terminal means, fourth logic gate means having an output part and first, second and third input parts, its second input connected to the output from said third amplifying gate means, said first and third inputs of said fourth logic gate connected to said enabling means and said memory means respectively, said output part of said fourth logic gate means connected to said first terminal means; whereby, when the direction of data transmission is established from one of said first and second terminal means to the other, said memory means applies and maintains an input to the respective logic gate associated with said direction of data transmission such that the output level thereof corresponds to the input level at said one terminal means when an enabling signal is applied to the first input part of said respective logic gate, said memory means further applying and maintaining an input to the other said logic gate such that the output thereof is constant regardless of the data input level at said other of said first and second terminal means, said memory means so functioning until the flow of data transmission in said established direction ceases;
 2. The invention as defined in claim 1 wherein the first and third amplifying gate means are inverting gates, and wherein the second and fourth logic gate means are NAND gates.
 3. The circuit of claim 2 wherein said memory means comprises seventh and eighth logic gate means each having first and second input parts, said first input part of said seventh logic gate means connected to said first terminal means and said second input part of said seventh logic gate means connected to said second input part of said fourth NAND gate means, said first input part of said eighth logic gate means connected to said second terminal means and said second input part of said eighth logic gate means connected to said second input part of said second NAND gate means, said memory means also comprises a fifth and sixth logic gate means cross connected as a storage element or flip-flop, the output part of said seventh logic gate means connected to a first input part of the fifth logic gate means, the output part of said fifth logic gate means connected to a second input part of the sixth logic gate means, said sixth logic gate means having its output part connected to a second input part of said fifth logic gate means and said sixth logic gate means having a first input part connected to the output part of said eighth logic gate means, the output parts of said fifth and sixth logic gate means being connected to the third input parts of said fourth and second NAND gate means respectively;
 4. The circuit as defined in claIm 3 wherein the seventh and eighth logic gate means are NAND gates and wherein the fifth and sixth logic gate means are OR gates with inverting input parts.
 5. The circuit as defined in claim 3 wherein the seventh and eighth logic gate means are NAND gates and wherein the fifth and sixth logic gate means are AND gates with inverting input parts.
 6. The circuit as defined in claim 3 wherein the seventh and eighth logic gate means are NAND gates and wherein the fifth and sixth logic gate means are NAND gates.
 7. The circuit as defined in claim 3 wherein the seventh and eighth logic gate means are NAND gates and wherein the fifth and sixth logic gate means are NOR gates.
 8. The invention as defined in claim 2 wherein said memory means comprises seventh and eighth logic gate means, each having first and second input parts, said first input part of said seventh logic gate means connected to said first terminal means and said second input part of said seventh logic gate means connected to said second input part of said fourth NAND gate means, said first input part of said eighth logic gate means connected to said second terminal means and said second input part of said eighth logic gate means connected to said second input part of said second NAND gate means, said memory means also comprises a fifth and a sixth logic gate means cross connected as a storage element or flip-flop, the output part of said seventh logic gate means connected to a first input part of the fifth logic gate means, the output part of said fifth logic gate means connected to a second input part of the sixth logic gate means, said sixth logic gate means having its output part connected to a second input part of said fifth logic gate means and said sxith logic gate means having a first input part connected to the output part of said eighth logic gate means, the output parts of said fifth and sixth logic gate means being connected to the third input parts of said second and fourth NAND gate means respectively.
 9. The circuit as defined in claim 8 wherein the seventh and eighth logic gate means are AND gates and wherein the fifth and sixth logic gate means are NOR gates.
 10. The circuit as defined in claim 8 wherein the seventh and eighth logic gate means are AND gates and wherein the fifth and sixth logic gate means are NAND gates.
 11. The circuit as defined in claim 8 wherein the seventh and eighth logic gate means are AND gates and wherein the fifth and sixth logic gate means are OR gates with inverting input parts.
 12. The circuit as defined in claim 8 wherein the seventh and eighth logic gate means are AND gates and wherein the fifth and sixth logic gate means are AND gates with inverting input parts.
 13. The invention as defined in claim 1 wherein the first and third amplifying gate means are non-inverting gates, and wherein the second and fourth logic gate means are NOR gates.
 14. A bi-directional bus switch circuit comprising first and second terminal means for series connection into a bus-line, each of said first and second terminal means resistively coupled to means for connection to a power supply rail, said first terminal means connected through a fifth controllable switch means to means for connection to a reference ground potential rail and said second terminal means connected through a seventh controllable switch means to means for connection to said reference ground potential rail, fifth and sixth diode means series connected between said first terminal means and the control electrode of a third controllable switch means, second and third diode means series connected between said second terminal means and the control electrode of a fourth controllable switch means, fifth resistive means connected between means for connection to said potential supply rail and fourth diode means, the junction between said fifth resistive means and said fourth diode means being connected through said third controllable switch means to the control Electrode of an eighth controllable switch means, said junction between said fifth resistive means and said fourth diode means being further connected through first and sixth controllable switch means to means for connection to said reference ground potential rail, sixth resistive means connected between means for connection to said potential supply rail and first diode means, the junction between said sixth resistive means and said first diode means being connected through said fourth controllable switch means to the control electrode of said sixth controllable switch means, said junction between said sixth resistive means and said first diode means being further connected through second and said eighth controllable switch means to means for connection to said reference ground potential rail, the side of said fourth diode means remote from said fifth resistive means connected to the control electrode of said second controllable switch means and the side of said first diode means remote from said sixth resistive means connected to the control electrode of said first controllable switch means, the junction of said first and sixth controllable switch means connected to the control electrode of said fifth controllable switch means and the junction of said second and eighth controllable switch means connected to the control electrode of said seventh controllable switch means, third and fourth resistive means connecting the junctions between said fifth and sixth and said second and third diode means respectively to means for connection to said potential supply rail and means connected to the control electrodes of said third and fourth controllable switch means for connection to a pulse potential supply means for selectively enabling and disabling said third and fourth controllable switch means.
 15. The circuit of claim 14 wherein said controllable switch means are bipolar transistors.
 16. The circuit of claim 14 wherein said diode means are diodes.
 17. The circuit of claim 14 wherein said resistive means are resistors. 